Los Gatos, CA, United States of America

Tao Wei

This inventor holds 2 USPTO granted patents and 4 published patent applications. Top assignees: Bourns Incorporated, Powerwyse, Inc.. Active years: 2016-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tao Wei. Retrieved from https://idiyas.com/inventor/tao-wei-h91hkohs

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 1.3

ph-index = 1


Company Filing History:


Years Active: 2016-2017

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2 patents (USPTO):Explore Patents

Title: Tao Wei: Semiconductor Device Inventor

Introduction

Tao Wei is an inventor associated with Los Gatos, California. His patent work concerns semiconductor devices, including transient voltage suppressors and high-voltage power MOSFETs. The supplied information lists 2 patents and identifies work with Powerwyse, Inc. and Bourns Incorporated.

Latest Patents

**Integration of an Auxiliary Device with a Clamping Device in a Transient Voltage Suppressor.** This invention describes monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions that conduct under reverse bias. It uses three epitaxial layers: the top two form the low-capacitance junctions, while the top layer also forms the low-resistance junction. Buried structures at the interfaces between the epitaxial layers help create a highly doped region extending from the low-resistance junction toward the substrate. This region provides a low-resistance path for current, while dopant diffusion during thermal processing forms the high-doping region.

**System and Method for Fabricating High Voltage Power MOSFET.** This patent describes a high-voltage power MOSFET with a semiconductor substrate, source, drain region, and one or more drain layers. An insulating layer covers at least part of the body region and lies over the drain layers. A voltage-regulating layer can shape voltage distribution in those layers, helping deplete charge carriers to increase blocking voltage when the device is off and accumulate carriers to reduce on-state resistance.

Career Highlights

The provided career information connects Wei with Powerwyse, Inc. and Bourns Incorporated. His listed inventions address semiconductor design challenges involving current flow, capacitance, voltage blocking, and resistance.

Collaborations

Andrew John Morrish is identified as Wei’s coworker. The supplied information does not specify their particular projects or patent contributions together.

Conclusion

Tao Wei’s listed patent work focuses on semiconductor structures designed to balance electrical performance, including low capacitance, low resistance, and high-voltage operation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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