Bourns Incorporated

Powerwyse, Inc.

Tao Wei

Andrew John Morrish

Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.

Integration of an auxiliary device with a clamping device in a transient voltage suppressor

A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.

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Los Gatos, CA, United States of America

Tao Wei