Tokyo, Japan

Takeshi Nagai

This inventor holds 126 USPTO granted patents, plus 2 CIPO patents, primarily in Semiconductor Technology (CPC class G06K9-36). Top assignees: Kabushiki Kaisha Toshiba, Ajinomoto Co., Ltd., Smc Kabushiki Kaisha. Active years: 1991-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takeshi Nagai. Retrieved from https://idiyas.com/inventor/takeshi-nagai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0


Average Co-Inventor Count = 3.3

ph-index = 20

Forward Citations = 1,675(Granted Patents)

Forward Citations (Not Self Cited) = 1,502(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Murayama, JP (2002)
  • Kawasaki, JP (1993 - 2007)
  • Tokorozawa, JP (2006 - 2009)
  • Saitama-ken, JP (2008 - 2009)
  • Tokyo-to, JP (2000 - 2010)
  • Saitama, JP (2010)
  • Higashi-Murayama, JP (1998 - 2011)
  • Yokohama, JP (2001 - 2011)
  • Kanagawa, JP (2006 - 2012)
  • Tokyo, JP (1991 - 2017)

Company Filing History:


Years Active: 1991-2017

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Areas of Expertise:
Semiconductor Device
Integrated Circuit
Error Correction
Optical Communication
Data Transmission
Moving-Picture Coding
ECC Function
Texture Image Compression
Coding Apparatus
Decoding Apparatus
Mobile Terminal
Synchronous Storage
126 patents (USPTO):Explore Patents

Title: Innovator Takeshi Nagai: Master of Semiconductor Technology

Introduction: Takeshi Nagai, a prolific inventor based in Tokyo-to, Japan, holds an impressive 126 patents throughout his career. His work primarily focuses on semiconductor devices, showcasing his expertise and innovative spirit in the field of technology.

Latest Patents: Among his latest inventions are cutting-edge semiconductor devices and corresponding manufacturing methods. One notable patent involves a semiconductor device that features a substrate containing a well region of a specific conductivity type, alongside an element isolation insulating film nestled within the well region. This innovative design incorporates an island-shaped active region, flanked by two first gate structures that comprise a lower gate insulating film, a gate insulating film with a high dielectric constant, a first gate electrode film made from metal material, and a second gate electrode film. The arrangement of the gates is meticulously ordered to optimize device functionality.

Another significant patent outlines a semiconductor device comprising a gate electrode positioned on a gate insulating film atop a semiconductor substrate. It includes a first sidewall insulating film adorning the side surface of the gate electrode, and source and drain regions imbued with pocket diffusion layers and diffusion layers of varying conductivity types. This invention emphasizes precision in the layering of materials to enhance the performance of semiconductor devices.

Career Highlights: Takeshi Nagai has made substantial contributions during his time at esteemed companies, including Kabushiki Kaisha Toshiba and Ajinomoto Co., Ltd. His innovative designs and patents have played a crucial role in advancing semiconductor technology, establishing him as a key figure in the industry.

Collaborations: Throughout his career, Nagai has had the opportunity to collaborate with notable coworkers, including Yoshihiro Kikuchi and Takeshi Chujoh. These collaborations have undoubtedly spurred innovative ideas and technological advancements in their joint projects.

Conclusion: With a remarkable portfolio of 126 patents, Takeshi Nagai exemplifies the spirit of innovation in the semiconductor industry. His latest inventions highlight his commitment to advancing technology and improving device performance. As a seasoned inventor, his work will continue to inspire future generations in the realm of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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