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Kanagawa, Japan

Takeshi Asamura

This inventor holds 6 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2000-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takeshi Asamura. Retrieved from https://idiyas.com/inventor/takeshi-asamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 66.7

Average Co-Inventor Count = 1.1

ph-index = 2

Forward Citations = 20(Granted Patents)

Location History:

Chigasaki, JP (2000)
Kanagawa-ken, JP (2001 - 2003)
Yokohama, JP (2005)

Company Filing History:

6 out of 53,250

Kabushiki Kaisha Toshiba

Years Active: 2000-2005

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6925343 - FLOW CONVERSION SYSTEM FOR A MANUFACTURING PROCESS, METHOD FOR CONVERTING A PROCESS FLOW, SYSTEM FOR CONTROLLING MANUFACTURING PROCESS, METHOD FOR CONTROLLING A MANUFACTURING PROCESS AND A COMPUTER PROGRAM PRODUCT (2005-08-02),

2. 6521528 - Semiconductor device and method of making thereof (2003-02-18),

3. 6512278 - Stacked semiconductor integrated circuit device having an inter-electrode barrier to silicide formation (2003-01-28),

4. 6475853 - Stacked semiconductor integrated circuit device and manufacturing method thereof (2002-11-05),

5. 6188136 - Semiconductor device including a wiring layer having a non-doped or high resistivity polycrystal silicon portion (2001-02-13),

6. 6074938 - Method of forming a semiconductor device comprising a dummy polysilicon (2000-06-13),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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