Kanagawa, Japan

Takeshi Asamura

This inventor holds 6 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2000-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takeshi Asamura. Retrieved from https://idiyas.com/inventor/takeshi-asamura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 66.7

Average Co-Inventor Count = 1.1

ph-index = 2

Forward Citations = 20(Granted Patents)


Location History:

  • Chigasaki, JP (2000)
  • Kanagawa-ken, JP (2001 - 2003)
  • Yokohama, JP (2005)

Company Filing History:


Years Active: 2000-2005

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6 patents (USPTO):Explore Patents

Title: Takeshi Asamura: Manufacturing Process and Semiconductor Inventions.

Introduction

Takeshi Asamura is an inventor associated with Kabushiki Kaisha Toshiba and based in Kanagawa, Japan. His listed work spans manufacturing-process control and semiconductor-device design. He is credited with 6 patents.

Latest Patents

The supplied patent information highlights inventions addressing both the organization of manufacturing workflows and the construction of semiconductor devices.

“Flow Conversion System for a Manufacturing Process,” “Method for Converting a Process Flow,” “System for Controlling Manufacturing Process,” “Method for Controlling a Manufacturing Process,” and “A Computer Program Product” describe a system for generating and selecting process flows. The system decomposes a target process into lower-level processes, substitutes compatible alternatives, checks which processes are available at production facilities, and selects a flow using defined attributes. Stored tables provide the information needed for decomposition, compatibility, availability, and attribute evaluation.

“Semiconductor Device and Method of Making Thereof” concerns a semiconductor substrate with two regions and distinct wiring structures. The described wiring layers use different polycrystalline-silicon compositions and metal-silicide thicknesses, including a thicker silicide layer in the second wiring structure.

Career Highlights

Asamura’s listed patents reflect work in two technical areas: manufacturing-process planning and control, and semiconductor-device fabrication. The manufacturing invention uses structured process data to identify feasible production flows, while the semiconductor invention specifies material and layer arrangements for device wiring.

Collaborations

The supplied information names Koji Kitajima and Shoichi Harakawa as Asamura’s coworkers. It does not specify their roles in the listed inventions.

Conclusion

Takeshi Asamura’s patent portfolio, as described in the supplied information, brings together methods for selecting manufacturing workflows and designs for semiconductor wiring. His work is associated with Kabushiki Kaisha Toshiba and includes 6 patents.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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