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For the Inventor, By the Inventor

Tokyo, Japan

Takehiko Tsuchiya

This inventor holds 10 USPTO granted patents. Top assignees: Kabushiki Kaisha Toshiba, Other. Active years: 2002-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takehiko Tsuchiya. Retrieved from https://idiyas.com/inventor/takehiko-tsuchiya

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 10

% Patents Active = 50.0

Average Co-Inventor Count = 1.1

ph-index = 4

Forward Citations = 41(Granted Patents)


Location History:

  • Musashino, JP (2002)
  • Tokyo, JP (2005 - 2009)
  • Kanagawa-ken, JP (2007 - 2011)
  • Yokohama, JP (2013 - 2014)
  • Kanagawa, JP (2014)

Company Filing History:

goldMedal9 out of 53,286 
 
Kabushiki Kaisha Toshiba
 patents
silverMedal1 out of 834,601 
Other
 patents

Years Active: 2002-2014

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10 patents (USPTO):Explore Patents
1. 8856556 - System and method for verifying and maintaining consistency between an intended power mode and an actual power mode in a semiconductor integrated circuit (2014-10-07),
2. 8700927 - Semiconductor integrated circuit, interconnect, and computer readable medium storing medium storing control program (2014-04-15),
3. 8516419 - Verification device of semiconductor integrated circuit, verification method of semiconductor integrated circuit, and computer readable medium storing verification program of semiconductor integrated circuit (2013-08-20),
4. 7908577 - Apparatus and method for analyzing circuit specification description design (2011-03-15),
5. 7519939 - Method and program for supporting register-transfer-level design of semiconductor integrated circuit (2009-04-14),
6. 7263478 - System and method for design verification (2007-08-28),
7. 7219312 - Method and program for supporting register-transfer-level design of semiconductor integrated circuit (2007-05-15),
8. 7107190 - Circuit designing apparatus, circuit designing method, and computer readable recording medium storing a circuit designing program (2006-09-12),
9. 6851102 - Method and program for supporting register-transfer-level design of semiconductor integrated circuit (2005-02-01),
10. 6449750 - Design verification device, method and memory media for integrated circuits (2002-09-10),

Title: Takehiko Tsuchiya: Innovator in Semiconductor Technology

Introduction

Takehiko Tsuchiya is a prominent inventor based in Tokyo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work focuses on enhancing the efficiency and functionality of semiconductor integrated circuits.

Latest Patents

One of Tsuchiya's latest patents is a system and method for verifying and maintaining consistency between an intended power mode and an actual power mode in a semiconductor integrated circuit. This innovative design support system includes a partial power control mechanism that utilizes a simulation program to perform partial power control based on circuit descriptions and power specifications. Additionally, it features a power mode transition detection program that records power mode information during execution and a check program to ensure the examined power mode is utilized correctly.

Another notable patent involves a semiconductor integrated circuit that comprises an adjuster and a controller. The adjuster temporarily holds data transmitted and received among multiple devices, while the controller manages power consumption based on changes in location information.

Career Highlights

Throughout his career, Takehiko Tsuchiya has worked with notable companies, including Kabushiki Kaisha Toshiba. His expertise in semiconductor technology has allowed him to develop innovative solutions that address complex challenges in the industry.

Collaborations

One of his key collaborators is Eiichi Yano, with whom he has worked on various projects to advance semiconductor technology.

Conclusion

Takehiko Tsuchiya's contributions to semiconductor technology through his patents and collaborations highlight his role as a leading inventor in the field. His innovative solutions continue to influence the development of efficient semiconductor integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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