The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2002

Filed:

Jan. 14, 2000
Applicant:
Inventor:

Takehiko Tsuchiya, Musashino, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

To provide a design verification device, a method and a memory medium therefor, for a semiconductor integrated circuit, capable of effectively introducing the formal verification in a higher-level design and capable of constructing a high-speed function verification environment with high verification assurance. A design verification device, a method and a memory medium therefor, for a semiconductor integrated circuit, has a function verification system which has an input of a circuit description before an alteration and a circuit description after the alteration and identifies an altered portion according to a disagreed portion, wherein formal verification is carried out for a circuit description that can assure an agreement with a key point corresponding to an output of a register and an input and an output of a signal in the circuit descriptions before and after the alteration, and verification is carried out by utilizing an event-driven simulation for a circuit description that cannot assure an agreement or equivalence of the key point.


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