Takako Ohashi

Title: Takako Ohashi: Semiconductor Interconnect and Device Layout Innovations

Introduction

Takako Ohashi is an inventor based in Shiga, Japan, whose patent work concerns semiconductor integrated circuits and device layout design. She is associated with Panasonic Corporation and holds 2 patents.

Latest Patents

Ohashi’s listed patents address interconnect design and semiconductor device layouts.

“Interconnect Structure of Semiconductor Integrated Circuit and Semiconductor Device Including the Same” describes shifting empty spaces between parallel power-supply interconnect segments to disperse local increases in resistance. This approach is intended to reduce the effect of voltage drops while respecting limits on interconnect length and occupied area.

“Semiconductor Device and Semiconductor Device Layout Designing Method” describes a device with cells that include an antenna protection element and other cells, alongside two dummy patterns in a layer above them. The patterns overlap different types of cells and follow different layout rules.

Career Highlights

Ohashi’s patent portfolio reflects work on practical semiconductor design challenges, including power-supply interconnect resistance, voltage drop, antenna protection, and layout rules for dummy patterns. Her listed affiliation is Panasonic Corporation.

Collaborations

Ohashi’s listed coworkers include Yoichi Matsumura and Chie Kabuo.

Conclusion

Takako Ohashi’s two patents highlight semiconductor innovations focused on improving interconnect behavior and refining device layout design.