The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2013

Filed:

Jun. 27, 2011
Applicants:

Yoichi Matsumura, Kyoto, JP;

Chie Kabuo, Kyoto, JP;

Takako Ohashi, Shiga, JP;

Tadafumi Kadota, Osaka, JP;

Kazuhiko Fujimoto, Kanagawa, JP;

Hirofumi Miyashita, Osaka, JP;

Inventors:

Yoichi Matsumura, Kyoto, JP;

Chie Kabuo, Kyoto, JP;

Takako Ohashi, Shiga, JP;

Tadafumi Kadota, Osaka, JP;

Kazuhiko Fujimoto, Kanagawa, JP;

Hirofumi Miyashita, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.


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