Tsuchiura, Japan

Tadashi Tachibana


Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 55(Granted Patents)


Location History:

  • Miho, JP (1987 - 1989)
  • Tsuchiura, JP (1989 - 1998)
  • Miho-mura, JP (2000)

Company Filing History:


Years Active: 1987-2000

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6 patents (USPTO):Explore Patents

Title: Innovations of Tadashi Tachibana

Introduction

Tadashi Tachibana is a notable inventor based in Tsuchiura, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 6 patents. His work has been instrumental in advancing memory device technology.

Latest Patents

One of his latest patents is a semiconductor memory device having a back gate voltage controlled delay. This innovative device includes an address buffer, a pre-decoder circuit, and a memory array, all working in conjunction to enhance performance. The design features a voltage generator that produces a back gate voltage, which is crucial for controlling the delay in the address transition detector pulse generator circuit. Another notable patent is the matched delay word line strap, which conserves layout area by ensuring that the total resistance of conductors connected to each signal source remains the same, thereby maintaining consistent signal delay.

Career Highlights

Tadashi Tachibana is currently employed at Texas Instruments Corporation, where he continues to develop cutting-edge technologies. His expertise in semiconductor memory devices has positioned him as a key player in the industry.

Collaborations

He has collaborated with esteemed colleagues such as Shunichi Sukegawa and Masashi Hashimoto, contributing to various projects that push the boundaries of semiconductor technology.

Conclusion

Tadashi Tachibana's innovative work in semiconductor technology and his contributions to memory devices highlight his importance in the field. His patents reflect a commitment to advancing technology and improving device performance.

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