Kasugai, Japan

Tadashi Asai

This inventor holds 1 USPTO granted patent. Top assignee: Fujitsu Corporation. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tadashi Asai. Retrieved from https://idiyas.com/inventor/tadashi-asai-e0hx8v5v

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 8.0

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: The Innovations of Tadashi Asai

Introduction

Tadashi Asai is a notable inventor based in Kasugai, Japan. He has made significant contributions to the field of semiconductor technology. His work focuses on enhancing the reliability and efficiency of semiconductor memory devices.

Latest Patents

Tadashi Asai holds a patent for a self-testing circuit in a semiconductor memory device. This innovative device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit features a comparison circuit that compares write data with read data for both normal and redundant memory blocks. Additionally, a decision circuit determines if the semiconductor memory device is functioning properly based on multiple comparison result signals.

Career Highlights

Asai is currently employed at Fujitsu Corporation, where he continues to develop cutting-edge technologies in semiconductor memory. His expertise in this area has positioned him as a valuable asset to his team and the company.

Collaborations

Throughout his career, Tadashi Asai has collaborated with talented individuals such as Kenji Togashi and Morihiko Hamada. These partnerships have fostered innovation and contributed to the advancement of semiconductor technology.

Conclusion

Tadashi Asai's work in semiconductor memory devices exemplifies the importance of innovation in technology. His contributions have the potential to enhance the performance and reliability of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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