Tracy, CA, United States of America

Surya P Varanasi

This inventor holds 7 USPTO granted patents. Top assignee: Lsi Logic Corporation. Active years: 2000-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Surya P Varanasi. Retrieved from https://idiyas.com/inventor/surya-p-varanasi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 4

Forward Citations = 172(Granted Patents)


Company Filing History:


Years Active: 2000-2003

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7 patents (USPTO):Explore Patents

Title: Innovations of Surya P Varanasi

Introduction

Surya P Varanasi is a notable inventor based in Tracy, California. He has made significant contributions to the field of video processing technology, particularly in the development of systems that enhance the decoding of MPEG compliant video bitstreams. With a total of 7 patents to his name, Varanasi's work has had a substantial impact on the industry.

Latest Patents

One of his latest patents is an IDCT processor designed for decoding MPEG compliant video bitstreams that meet 2-frame and letterboxing requirements. This innovative system and method for performing an inverse discrete cosine transform (IDCT) is IEEE compliant and efficiently transforms one block (8×8) of pixels in just 64 cycles. The IDCT processor receives DCT input, produces the matrix (QX Q)P, or X P, in IDCT Stage 1, and stores the result in transpose RAM. The subsequent IDCT Stage 2 performs a transpose of the result from Stage 1 and multiplies it by P, completing the IDCT process and yielding the IDCT output. The system performs a matrix function QX Q, where X represents the DCT data and Q is a predetermined diagonal matrix. The resultant value is adjusted by discarding selected bits, followed by post-multiplication with elements of a predetermined P matrix. This process includes conversion, storing functions, and sign changes to obtain QX QP, completing the first stage processing before passing it to transpose RAM. The system then initiates IDCT Stage 2, performing a matrix transpose of QX QP, yielding (QX QP). The system converts and clips data, post-multiplies the result by the P matrix, and performs additional conversions and buffer additions to obtain the final elements of (QX QP) P. The data is right-shifted seven bits with roundoff, ensuring truncation to values between -256 and 255.

Another significant patent involves an architecture and method for inverse quantization of discrete cosine transform coefficients in MPEG decoders. This inverse quantizer is designed with a reduced bit-width, receiving quantized DCT coefficients in sign+magnitude form with 1+11 bits of resolution. It produces reconstructed DCT coefficients with the same resolution. Although this is less than the theoretical minimum bit-width required by the MPEG standard, certain IDCT implementations

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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