The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2000

Filed:

Jul. 31, 1997
Applicant:
Inventors:

Surya P Varanasi, Tracy, CA (US);

Satish Soman, Cupertino, CA (US);

Tai Jing, Palo Alto, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ; H04B / ;
U.S. Cl.
CPC ...
375240 ; 348403 ;
Abstract

A system and method for decoding an MPEG video bitstream comprises, comprising a macroblock core (MBCORE) which processes video bitstream data and computes discrete cosine transform data and a parser which parses the video bitstream macroblocks into multiple data blocks used in subsequent stages of decoding. fixed length data words comprising variable length objects using a novel rotating register arrangement. A multistage transformation/motion compensation core (TMCCORE) uses intermediate memory. The IDCT first stage has the ability to operate on a first data block while the second stage simultaneously operates on a second data block. The TMCCORE receives the discrete cosine transform data from the MBCORE and calculates and reconstructs a frame therefrom using motion compensation. The MBCORE can operate on data from a first macroblock while the TMCCORE simultaneously operates on data from a second macroblock. The TMCCORE reconstructs the picture from one macroblock while the IDCT first and second stages simultaneously operate on data from the macroblock. Additionally, a horizontal and vertical half pixel compensation arrangement is included which has multiple adders and multiplexers.


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