San Jose, CA, United States of America

Sungju Son

This inventor holds 3 USPTO granted patents. Top assignee: Skhynix Inc.. Active years: 2014-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sungju Son. Retrieved from https://idiyas.com/inventor/sungju-son

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2014-2015

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3 patents (USPTO):Explore Patents

Title: Sungju Son: Semiconductor Inventor in San Jose

Introduction

Sungju Son is an inventor based in San Jose, California, whose patent work focuses on semiconductor memory circuitry. His listed portfolio includes 3 patents, with two described inventions concerning e-fuse array circuits. He is associated with SK hynix Inc.

Latest Patents

Son’s latest listed patents address the design and operation of e-fuse array circuits.

The first e-fuse array circuit patent describes an arrangement combining a vertical-gate e-fuse transistor with a buried-gate selection transistor. The e-fuse transistor receives a program-gate voltage, while the selection transistor controls the electrical connection between a terminal of the e-fuse transistor and a bit line.

The second e-fuse array circuit patent describes parallel program-gate and word-line gate lines covered by a metal line. Multiple contact plugs connect the metal line to the program-gate line at specified intervals.

Career Highlights

Son’s listed inventions reflect work on circuit structures for e-fuse arrays, including transistor configurations and interconnect arrangements. These designs concern how programming signals and bit-line connections are managed within semiconductor circuitry.

Collaborations

The provided information lists Youncheul Kim and Sungho Kim as Son’s coworkers. It does not specify their roles or identify particular joint projects.

Conclusion

Sungju Son’s listed patent work centers on e-fuse array circuit designs, and his portfolio includes 3 patents.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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