The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Jun. 27, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Sungju Son, San Jose, CA (US);
Youncheul Kim, San Jose, CA (US);
Sungho Kim, Gyeonggi-do, KR;
Dongue Ko, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01); G11C 17/16 (2006.01); G11C 17/00 (2006.01); G11C 29/02 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 17/16 (2013.01); H01L 23/5256 (2013.01); G11C 17/00 (2013.01); G11C 17/165 (2013.01); G11C 29/027 (2013.01); G11C 29/787 (2013.01); G11C 2229/763 (2013.01);
Abstract
An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.