Icheon, South Korea

Sul Hwan Lee

This inventor holds 1 USPTO granted patent. Top assignee: Hynix Semiconductor Inc.. Active years: 2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sul Hwan Lee. Retrieved from https://idiyas.com/inventor/sul-hwan-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2016

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1 patent (USPTO):Explore Patents

Title: Innovations of Sul Hwan Lee in Semiconductor Technology

Introduction: Sul Hwan Lee is a notable inventor based in Icheon-si, South Korea. He has made significant contributions to the field of semiconductor technology. His innovative methods have the potential to enhance the efficiency and performance of semiconductor devices.

Latest Patents: Sul Hwan Lee holds a patent for a "Method for fabricating semiconductor device." This method involves forming at least two gate patterns on a substrate and creating sidewalls that surround these gate patterns. The sidewalls extend above the upper surface of the gate patterns. Additionally, the method includes forming a first conducting material in designated spaces above the gate patterns and between the sidewalls, as well as between the gate patterns. This innovative approach is crucial for advancing semiconductor fabrication techniques.

Career Highlights: Sul Hwan Lee is currently associated with Hynix Semiconductor Inc., a leading company in the semiconductor industry. His work at Hynix has allowed him to contribute to cutting-edge technologies and advancements in semiconductor manufacturing.

Collaborations:

Conclusion: Sul Hwan Lee's contributions to semiconductor technology through his innovative patent demonstrate his expertise and commitment to advancing the field. His work continues to influence the development of more efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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