Sukriti Khanna

Title: Innovator Sukriti Khanna: Pioneering Static Timing Analysis

Introduction

Sukriti Khanna is a notable inventor based in New Delhi, India. She has made significant contributions to the field of integrated circuits, particularly in static timing analysis. Her innovative work has led to the development of a patent that enhances the efficiency of circuit analysis.

Latest Patents

Sukriti Khanna holds a patent titled "Circuit stage credit based approaches to static timing analysis of integrated circuits." This patent focuses on static timing analysis (STA) of circuits. The STA involves determining graph-based analysis (GBA) delays of timing paths within the circuit. Additionally, path-based analysis (PBA) delays of a subset of timing paths are determined to generate circuit stage credit values for circuit stages. These credit values can be utilized to adjust GBA delays of the timing paths. Furthermore, prediction functions are employed to estimate PBA delays, thereby avoiding the need to determine actual PBA delays.

Career Highlights

Sukriti is currently associated with Cadence Design Systems, Inc., where she applies her expertise in circuit design and analysis. Her work has been instrumental in advancing the capabilities of integrated circuit technology.

Collaborations

Some of her coworkers include Umesh Gupta and Naresh Kumar, who contribute to the collaborative environment at Cadence Design Systems, Inc.

Conclusion

Sukriti Khanna's innovative contributions to static timing analysis exemplify her commitment to advancing technology in integrated circuits. Her patent reflects her expertise and dedication to improving circuit analysis methodologies.