Cadence Design Systems, Inc.

Sukriti Khanna

Naresh Kumar

Rakesh Agarwal

Umesh Gupta

Ritika Govila

Jayant Sharma

The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.

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New Delhi, India

Sukriti Khanna