Su Juan Wang

Title: Su Juan Wang: Memory-Access Innovation at Micron Technology

Introduction

Su Juan Wang is an inventor based in Shanghai, China, and is associated with Micron Technology Incorporated. Her patent work addresses memory-access performance, particularly how a system handles mismatches between logical translation units.

Latest Patents

The provided information identifies one patent for Su Juan Wang: “Reducing Read Latency Based on Logical Translation Unit Mismatch Statuses.” The invention describes receiving a memory-access command for a logical block address (LBA) from a high-speed processing device and reading data associated with multiple LBAs from a memory device into a data segment. The system determines the status of each LBA in that segment. When one or more LBAs have a logical translation unit mismatch status, the corresponding data is provided to the processing device. The device then returns an updated data segment containing data for the requested LBA, which the system uses to perform the memory-access operation. This approach is designed to reduce read latency when logical translation unit mismatches occur.

Career Highlights

Wang’s listed patent reflects work on memory systems and the coordination of data between storage devices and high-speed processing devices. The supplied information associates her with Micron Technology Incorporated and records 1 patent.

Collaborations

The named coworkers are Kun Jiang and Yu Long Guan. The provided information does not specify their roles or the nature of their collaboration with Wang.

Conclusion

Su Juan Wang’s recorded invention focuses on reducing read latency by responding to logical translation unit mismatches during memory access, highlighting a practical contribution to storage-system performance.