Jeollabuk-do, South Korea

Su Jeong Jeon

This inventor holds 1 USPTO granted patent. Top assignee: Electronics and Telecommunications Research Institute. Active years: 2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Su Jeong Jeon. Retrieved from https://idiyas.com/inventor/su-jeong-jeon

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2015

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Su Jeong Jeon: Inventor in Semiconductor Packaging

Introduction

Su Jeong Jeon is an inventor associated with the Electronics and Telecommunications Research Institute in Jeollabuk-do, South Korea. Her work includes a patent on fabricating solder-on-pad structures and using them in flip-chip bonding.

Latest Patents

Jeon is named on 1 patent: “Method of Fabricating a Solder-on-Pad Structure and Flip-Chip Bonding Method Using the Same.” The method describes coating a substrate with a solder bump maker containing resin and solder powder, then heating it below the solder powder’s melting point so the powder aggregates on a pad. The resin is subsequently removed.

Career Highlights

The patent addresses a process for forming solder-on-pad structures, which can be used in flip-chip bonding. Jeon’s listed institutional affiliation is the Electronics and Telecommunications Research Institute.

Collaborations

Kwang-Seong Choi and Ho-eun Bae are identified as Jeon’s coworkers.

Conclusion

Su Jeong Jeon’s patent documents a solder-on-pad fabrication approach intended for flip-chip bonding, reflecting her work in electronic packaging technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…