This inventor holds 3 USPTO granted patents. Top assignees: Hamilton Sundstrand Corporation, Goodrich Actuation Systems Limited. Active years: 2025-2026.
Company Filing History:


Years Active: 2025-2026
Title: The Innovative Contributions of Stephen Potter
Introduction
Stephen Potter is a notable inventor based in Nuneaton, GB. He has made significant contributions to the field of programmable logic devices and microprocessor architectures. With a total of 3 patents, his work showcases a blend of creativity and technical expertise.
Latest Patents
Potter's latest patents include a "Scalable and modular bus controller including page memory PLD architecture." This invention features a bus controller-based page memory programmable logic device (PLD) architecture that comprises multiple PLD modules and a bus controller. The bus controller communicates with these modules through a universal bus interface, allowing for efficient data transfer. His second patent, "Hybrid microprocessor and programmable logic device (PLD)-based architecture including inter processor communication," describes a microprocessor-PLD hybrid architecture. This architecture facilitates communication between an IPC microprocessor and a PLD, enabling data read and write operations through a series of commands.
Career Highlights
Stephen Potter is currently employed at Hamilton Sundstrand Corporation, where he continues to innovate and develop advanced technologies. His work has significantly impacted the design and functionality of programmable logic devices and microprocessor systems.
Collaborations
Potter has collaborated with talented coworkers, including Rajesh Madathikandam and Robin David Hill. Their combined expertise has contributed to the successful development of innovative technologies in their field.
Conclusion
Stephen Potter's contributions to the field of technology through his patents and collaborations highlight his role as a leading inventor. His work continues to influence advancements in programmable logic devices and microprocessor architectures.