Hyderabad, India

Srinivasa Rao Mudaddla

This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Srinivasa Rao Mudaddla. Retrieved from https://idiyas.com/inventor/srinivasa-rao-mudaddla

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Srinivasa Rao Mudaddla: Inventor of a Dynamic Frequency-Supported TDM Interface

Introduction

Srinivasa Rao Mudaddla is an inventor based in Hyderabad, India, and works at Synopsys, Inc. His patent work addresses time-division multiplexing (TDM), a method for transmitting multiple data streams over a shared communication channel. He is credited with 1 patent.

Latest Patents

Mudaddla’s patent, “Dynamic Frequency Supported Time Division Multiplexing Interface,” describes a TDM device designed to handle user clock and data signals from multiple inputs. The system uses a first-in-first-out (FIFO) circuit and a transmitter operating in a fast clock domain. Multiplexing state machines combine the input signals into a multiplexed signal for transmission using a fast clock. At the receiving end, demultiplexing state machines process the signal, while a second FIFO circuit delivers the user data to multiple outputs.

Career Highlights

Mudaddla’s listed invention focuses on coordinating data transfer across different clock domains and supporting multiplexed communication. His work at Synopsys, Inc. places this contribution within the field of electronic design and semiconductor technology.

Collaborations

Tejinder Kumar and Shyam Kumar Reddy Cheruku are identified as Mudaddla’s coworkers. The available information does not specify their roles in developing the patented interface.

Conclusion

Srinivasa Rao Mudaddla’s patent describes a TDM interface that combines and separates multiple data streams using FIFO circuits and clock-domain-specific state machines.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…