Sreekanth G Pai

Title: Innovations by Sreekanth G Pai

Introduction

Sreekanth G Pai is a notable inventor based in Cochin, India. He has made significant contributions to the field of integrated circuit testing, holding a total of 4 patents. His work focuses on methods that enhance power efficiency during testing processes.

Latest Patents

One of his latest patents is titled "Clock gating for power reduction during testing." This method involves testing an integrated circuit device that includes components of first and second types. The innovation prevents power consumption by gating off the clock signal to components of the second type, which consume power even when inactive. This approach can be applied to individual components or entire clock tree branches, ensuring that only necessary components receive clock signals during testing.

Another significant patent is "Power-sensitive scan-chain testing." This method addresses the challenges of scan-chain testing in integrated circuits with resource constraints. By gating scan-chain paths designated as having resource constraints, Sreekanth's method reduces the rate of data propagation without affecting other paths. This innovation is particularly useful in scenarios where high power consumption or data congestion is a concern.

Career Highlights

Sreekanth G Pai is currently employed at Marvell Asia Pte., Ltd., where he continues to develop innovative solutions in integrated circuit technology. His expertise in power-sensitive testing methods has positioned him as a valuable asset in the field.

Collaborations

He collaborates with talented coworkers, including Balaji Upputuri and Kushal Kamal, who contribute to the innovative environment at Marvell Asia Pte., Ltd.

Conclusion

Sreekanth G Pai's contributions to integrated circuit testing through his patents demonstrate his commitment to innovation and efficiency. His work not only enhances testing methods but also significantly reduces power consumption in electronic devices.