Sreedhar Chalasani

Title: Sreedhar Chalasani: Innovator in Thread Scheduling Techniques

Introduction

Sreedhar Chalasani is a notable inventor based in Folsom, CA. He has made significant contributions to the field of computer architecture, particularly in thread scheduling techniques. His innovative work has led to the development of a patent that addresses critical issues in cache management.

Latest Patents

Sreedhar holds a patent titled "Load store bank aware thread scheduling techniques." This patent describes bank aware thread scheduling and early dependency clearing techniques. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoid bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. By implementing early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache. He has 1 patent to his name.

Career Highlights

Sreedhar Chalasani is currently employed at Intel Corporation, where he continues to innovate and contribute to advancements in technology. His work at Intel has positioned him as a key player in the development of efficient computing solutions.

Collaborations

Some of his notable coworkers include Abhishek R Appu and Joydeep Ray, who have collaborated with him on various projects within the company.

Conclusion

Sreedhar Chalasani's contributions to thread scheduling techniques exemplify the importance of innovation in technology. His patent work not only addresses existing challenges but also paves the way for future advancements in computer architecture.