The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Mar. 21, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek R. Appu, El Dorado Hills, CA (US);

Joydeep Ray, Folsom, CA (US);

Karthik Vaidyanathan, San Francisco, CA (US);

Sreedhar Chalasani, Folsom, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 12/0891 (2016.01); G06T 1/00 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/48 (2013.01); G06F 9/4806 (2013.01); G06F 9/4843 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5016 (2013.01); G06F 9/505 (2013.01); G06F 9/5061 (2013.01); G06F 12/0891 (2013.01); G06T 1/00 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01);
Abstract

Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.


Find Patent Forward Citations

Loading…