Liaoning, China

Sijia Li

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Ndtm US LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sijia Li. Retrieved from https://idiyas.com/inventor/sijia-li-md8wxmro

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Sijia Li and an Innovation in 3D NAND Memory

Introduction

Sijia Li is an inventor associated with Liaoning, China, and Intel Ndtm US LLC. Her patent work addresses a fabrication challenge in vertical 3D NAND memory: forming reliable wordline contacts in the staircase regions of a memory array.

Latest Patents

The supplied information lists one patent for Sijia Li: “Selective Etch Stop for Wordline Contacts in Vertical 3D NAND Staircase Regions.” The disclosed apparatus includes vertical 3D NAND strings, a staircase region, a polysilicon wordline, and a vertical wordline contact. An etch-stop material surrounds the contact and lies on the wordline, extending to the step’s outside corner while remaining absent from its sidewall and undercut at the corner. This arrangement is intended to support selective etching during fabrication. The patent record provided identifies 1 patent.

Career Highlights

The available information connects Li’s patent activity with Intel Ndtm US LLC. Her listed invention focuses on a specific structural feature of 3D NAND manufacturing rather than providing details about her broader career or professional history.

Collaborations

Zhiyuan Yu and Hongpeng Yu are identified as Li’s coworkers. The supplied information does not specify their roles in the patent or whether they collaborated on this invention.

Conclusion

Sijia Li’s listed patent concerns an etch-stop structure for wordline contacts in 3D NAND staircase regions, reflecting a focused contribution to memory-device fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…