Kota Samarahan, Malaysia

Shyh Yau Tein

This inventor holds 1 USPTO granted patent. Top assignee: X-Fab Global Services Gmbh. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shyh Yau Tein. Retrieved from https://idiyas.com/inventor/shyh-yau-tein

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Shyh Yau Tein: Innovator in Transistor Technology

Introduction

Shyh Yau Tein is a notable inventor based in Kota Samarahan, Malaysia. He has made significant contributions to the field of transistor technology, particularly with his innovative designs aimed at reducing flicker noise.

Latest Patents

Shyh Yau Tein holds a patent for a "Reduced flicker noise transistor layout." This invention includes a transistor with a diffusion region that has a drain, a source, and a channel situated between the drain and source. The design features an isolation region surrounding the diffusion region to provide electrical isolation. Additionally, the transistor incorporates a gate poly that overlaps at least part of the channel, with the diffusion region extending laterally beyond the gate poly in the channel width direction. This innovative layout is aimed at enhancing the performance of transistors in various applications.

Career Highlights

Shyh Yau Tein is currently employed at X-Fab Global Services GmbH, where he continues to develop cutting-edge technologies in semiconductor manufacturing. His work has been instrumental in advancing the capabilities of transistors, making them more efficient and reliable.

Collaborations

Some of his notable coworkers include Xuezhou Cao and Michaelina Ong, who contribute to the innovative environment at X-Fab Global Services GmbH.

Conclusion

Shyh Yau Tein's contributions to transistor technology exemplify the spirit of innovation in the field of electronics. His patent for a reduced flicker noise transistor layout showcases his commitment to enhancing the performance of semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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