San Jose, CA, United States of America

Shun-Miin (Sam) Wang

This inventor holds 3 USPTO granted patents. Top assignee: Syntest Technologies, Inc.. Active years: 2006-2009.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shun-Miin (Sam) Wang. Retrieved from https://idiyas.com/inventor/shun-miin-sam-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 6.0

ph-index = 3

Forward Citations = 95(Granted Patents)


Company Filing History:


Years Active: 2006-2009

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3 patents (USPTO):Explore Patents

Title: Innovations by Shun-Miin (Sam) Wang

Introduction

Shun-Miin (Sam) Wang is a notable inventor based in San Jose, CA, who has made significant contributions to the field of integrated circuits. With a total of three patents to his name, Wang's work focuses on enhancing the efficiency and effectiveness of scan-based integrated circuits.

Latest Patents

Wang's latest patents include a method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit. This innovation involves time-division demultiplexing and decompressing a compressed input stimulus provided at a selected data rate R1 into a decompressed stimulus driven at a selected data rate R2. The goal is to drive selected scan chains in a scan-based integrated circuit using multiple time-division demultiplexors and multiplexors, ultimately reducing test time, test cost, and scan pin count. Another significant patent is related to smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits. This method generates stimuli and test responses for testing faults in a scan-based integrated circuit, which contains multiple scan chains and clock domains. The process involves compiling the circuit into a sequential model, specifying input constraints, and generating stimuli based on an equivalent combinational circuit model.

Career Highlights

Wang is currently employed at Syntest Technologies, Inc., where he continues to innovate and develop advanced solutions for integrated circuits

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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