Hsinchu, Taiwan

Shu-Cheng Li

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shu-Cheng Li. Retrieved from https://idiyas.com/inventor/shu-cheng-li-yy127951

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Shu-Cheng Li and Semiconductor Interconnect Innovation.

Introduction

Shu-Cheng Li is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work concerns semiconductor connection structures designed to support electrical connections between vias while avoiding stacked-via arrangements.

Latest Patents

The provided information lists one patent for Li: “Via Connection Structure Having Multiple Via-to-Via Connections.” The invention describes a conductive structure positioned between and electrically contacting multiple via structures. The vias are laterally offset from adjacent vias, avoiding direct stacking, and each via connects to at least two other vias on a semiconductor-device level through conductive traces and footprints.

Career Highlights

Li’s listed patent reflects work on semiconductor interconnect design and methods of manufacture. The described structure provides multiple electrical paths among vias while arranging them laterally across the device.

Collaborations

The provided information identifies Ting-Yu Yeh and Chun-Hsien Wen as Li’s coworkers at Taiwan Semiconductor Manufacturing Company Limited.

Conclusion

Shu-Cheng Li’s listed invention addresses semiconductor connectivity through a laterally offset, multi-via structure, contributing a specific approach to interconnect design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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