La Jolla, CA, United States of America

Shashank Bansal

This inventor holds 1 USPTO granted patent. Top assignees: Northrop Grumman Systems Corporation, University of California. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shashank Bansal. Retrieved from https://idiyas.com/inventor/shashank-bansal-voc81a2e

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Shashank Bansal: Inventor of an Energy-Efficient Compute-in-Memory Circuit

Introduction

Shashank Bansal is an inventor based in La Jolla, California. His work includes a patent for an energy-efficient compute-in-memory architecture designed to improve multiply-and-accumulate operations in SRAM-based circuits.

Latest Patents

Bansal’s patent, “Energy Efficient Compute-in-Memory SRAM-C Circuit Architecture,” describes a capacitively coupled static random-access memory (SRAM-C) compute-in-memory circuit. The design combines SRAM cells that store bit values with capacitively coupled circuits and an energy recovery logic driver. The driver recovers signal energy using a ramped sinusoidal hot clock.

The capacitively coupled circuit uses two capacitors and four pairs of transistors. The patent describes how these components connect to support computation within the memory circuit. The architecture is intended to improve the energy efficiency and effectiveness of multiply-and-accumulate operations. Bansal has 1 patent.

Career Highlights

Bansal’s listed professional affiliations include Northrop Grumman Systems Corporation and the University of California. These organizations reflect experience across industry and academia.

Collaborations

Bansal’s listed coworker is Gert Cauwenberghs. Their association connects his work with research in computing and circuit design.

Conclusion

Shashank Bansal’s patented SRAM-C architecture focuses on reducing energy use in compute-in-memory circuits while supporting efficient multiply-and-accumulate operations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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