Cheonan, South Korea

Seunghwan Baek

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Seunghwan Baek. Retrieved from https://idiyas.com/inventor/seunghwan-baek-4gvzu8pd

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Seunghwan Baek and Semiconductor Packaging Innovation.

Introduction

Seunghwan Baek is an inventor based in Cheonan, South Korea. His patent work concerns semiconductor packaging, including structures designed to connect and support components within stacked packages. He is associated with Samsung Electronics Ltd.

Latest Patents

Baek is credited with 1 patent: “Semiconductor Package Structure Having Interposer Substrate, and Stacked Semiconductor Package Structure Including the Same.”

The invention describes a semiconductor chip mounted on a package substrate, with an interposer substrate positioned above the chip and connected through bumps. A separate support structure helps maintain spacing and provide support between the package substrate and the interposer. It includes a metal core ball surrounded by a ball-cover layer whose thickness gradually decreases toward the package substrate. The design addresses both electrical connection and mechanical support in a stacked semiconductor package.

Career Highlights

Baek’s listed patent highlights work on interposer-based packaging and the structural details that can support reliable connections in stacked semiconductor assemblies. His patent is associated with Samsung Electronics Ltd.

Collaborations

The listed coworkers associated with Baek are Sunchul Kim and Yonghyun Kim. Their names appear alongside his work on semiconductor package structures.

Conclusion

Seunghwan Baek’s patent reflects an engineering contribution to semiconductor packaging, combining interposer connections with a supporting structure for stacked package designs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…