Sergey Khaikin

Title: Sergey Khaikin and Electronic Design Verification

Introduction

Sergey Khaikin is an inventor associated with San Diego, California, and Cadence Design Systems, Inc. His patent work addresses verification challenges in complex electronic designs, particularly the detection of potential deadlocks.

Latest Patents

Khaikin is associated with 1 patent: “Method, System, and Computer Program Product for Verifying an Electronic Design Using Stall Prevention Requirements of Electronic Circuit Design Models of the Electronic Design.” The invention identifies cells and their stall-prevention requirements or transactions, then maps dependencies between them in a graph. It analyzes loops in that graph to detect potential deadlocks and can filter out false deadlocks. The analysis can be performed sequentially or in parallel for individual cells, helping divide the verification of a complex electronic system into manageable parts.

Career Highlights

Khaikin’s patent reflects work on methods for analyzing electronic circuit designs and identifying dependency patterns that may cause deadlocks. His association with Cadence Design Systems connects this work to a company focused on electronic design technologies.

Collaborations

Lawrence Loh is identified as Khaikin’s coworker. The available information does not specify their particular projects or contributions together.

Conclusion

Sergey Khaikin’s patented approach uses graph-based dependency analysis to help identify potential deadlocks in electronic designs and support the verification of complex systems.