Asan, South Korea

Seong-Gwon Jang

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Seong-Gwon Jang. Retrieved from https://idiyas.com/inventor/seong-gwon-jang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2020

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1 patent (USPTO):Explore Patents

Title: Seong-Gwon Jang and Memory Device Testing Innovation.

Introduction

Seong-Gwon Jang is an inventor associated with Asan, South Korea, and Samsung Electronics Co., Ltd. His patent work concerns memory-device testing and control.

Latest Patents

Jang is associated with 1 patent: “Memory Device with Test Circuit Which Generates Asynchronous Signal Based on Delay and Controls Peripheral Circuit Based on Asynchronous Signal, Operating Method of Memory Device, and Operating Method of Test System Including Memory Device.”

The invention describes a memory device with a memory cell array, a peripheral circuit, a test mode register set, and a test circuit. The register set stores a delay value. When the test circuit detects an externally received clock select signal, it uses the delay value to generate an asynchronous signal from an external clock and controls the peripheral circuit based on that signal. The peripheral circuit stores data in or reads data from the memory cell array.

Career Highlights

Jang’s listed patent reflects work on memory-device architecture and test operations. Its approach uses a stored delay value to coordinate asynchronous signaling and peripheral-circuit control during testing.

Collaborations

Jang is associated with Samsung Electronics Co., Ltd. His listed coworker is Joosung Yun.

Conclusion

Seong-Gwon Jang’s patent highlights a memory-testing innovation that uses delay-based asynchronous signaling to control peripheral circuitry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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