Samsung Electronics Co., Ltd.

Seong-Gwon Jang

Joosung Yun

A memory device includes a memory cell array, a peripheral circuit, a test mode register set, and a test circuit. The peripheral circuit stores data in the memory cell array or reads data from the memory cell array. The test mode register set stores a delay value. In response to detecting a clock select signal received from outside the memory device, the test circuit generates an asynchronous signal from a clock received from the outside based on the delay value, and controls the peripheral circuit based on the asynchronous signal.

Memory device with test circuit which generates asychronous signal based on delay and controls peripheral circuit based on asynchronous signal, operating method of memory device, and operating method of test system including memory device

Growing community of inventors

Asan-si, South Korea

Seong-Gwon Jang