Noida, India

Saurabh Verma

This inventor holds 1 USPTO granted patent. Top assignee: Atrenta, Inc.. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saurabh Verma. Retrieved from https://idiyas.com/inventor/saurabh-verma-jz560099

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Saurabh Verma - Innovator in Integrated Circuit Design

Introduction

Saurabh Verma is a notable inventor based in Noida, India. He has made significant contributions to the field of integrated circuit design. His innovative approach has led to the development of a unique patent that addresses common challenges in the design process.

Latest Patents

Saurabh Verma holds a patent titled "System and method for large multiplexer identification and creation in a design of an integrated circuit." This patent focuses on the efficient conversion of functional descriptions into multiplexers during the design of integrated circuits. By combining multiple multiplexers into a larger one, potential design problems can be identified early, preventing costly routing congestion issues later in the process. The patent emphasizes the importance of detecting multiplexing functionalities and merging them when possible to enhance circuit efficiency.

Career Highlights

Saurabh Verma is currently employed at Atrenta, Inc., where he continues to innovate in the field of integrated circuit design. His work has been instrumental in advancing methodologies that improve the efficiency and effectiveness of circuit designs.

Collaborations

Saurabh has collaborated with esteemed colleagues such as Tien-Chien Lee and Satrajit Pal. These collaborations have fostered a creative environment that encourages the exchange of ideas and innovative solutions.

Conclusion

Saurabh Verma's contributions to integrated circuit design through his patent and work at Atrenta, Inc. highlight his role as a key innovator in the field. His efforts in improving design methodologies are paving the way for more efficient integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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