Santa Clara, CA, United States of America

Santosh K Yachareni


Average Co-Inventor Count = 3.0

ph-index = 7

Forward Citations = 395(Granted Patents)


Company Filing History:


Years Active: 2001-2006

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12 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Santosh K Yachareni

Introduction

Santosh K Yachareni is a prominent inventor based in Santa Clara, CA. She has made significant contributions to the field of semiconductor memory devices, holding a total of 12 patents. Her work focuses on enhancing the efficiency and functionality of memory systems.

Latest Patents

Among her latest patents is a method and apparatus for pre-charging negative pump MOS regulation capacitors. This invention involves erasing a core memory cell using a negative gate voltage in a semiconductor memory device. The negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during the core cell erase operation. Additionally, she has developed a system and method to facilitate the stabilization of reference voltage signals in memory devices. This wait system provides a wait signal to delay the performance of operations relative to the memory cell, optimizing the overall functionality of the device.

Career Highlights

Throughout her career, Santosh has worked with notable companies, including Advanced Micro Devices Corporation. Her expertise in semiconductor technology has positioned her as a key player in the industry, contributing to advancements that benefit various applications.

Collaborations

Santosh has collaborated with several professionals in her field, including Edward V Bautista, Jr. and Kazuhiro Kurihara. These collaborations have further enriched her work and expanded the impact of her inventions.

Conclusion

Santosh K Yachareni's innovative contributions to semiconductor memory technology demonstrate her expertise and commitment to advancing the field. Her patents reflect a deep understanding of complex systems and a drive to improve memory device performance.

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