Cheongju, South Korea

Sangho Lee

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Magnachip Semiconductor, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sangho Lee. Retrieved from https://idiyas.com/inventor/sangho-lee-whaolzm1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Sangho Lee and His Buffer Circuit Innovation.

Introduction

Sangho Lee is an inventor associated with Cheongju, South Korea, and Magnachip Semiconductor, Inc. His patent work includes a circuit design intended to improve slew-rate performance in electronic systems.

Latest Patents

Lee is credited with 1 patent: “Buffer Circuit Having Enhanced Slew Rate.” The invention describes a buffer circuit with an input stage that provides or receives differential current based on the difference between input and output voltages. A load stage applies gate voltages to two output transistors, while the output stage regulates the output voltage. The design also includes a slew-rate compensation circuit, an offset-control signal output stage, and an offset-blocking circuit that can switch off a current source in the compensation circuit.

Career Highlights

Lee’s listed patent reflects work on circuit architecture and signal-transition performance. The design coordinates the input, load, output, and compensation stages to manage the output voltage and slew rate.

Collaborations

Lee’s listed coworker is Hyoungkyu Kim. Both are associated with the patent, which identifies Magnachip Semiconductor, Inc. as the company connected to Lee’s work.

Conclusion

Sangho Lee’s patent presents a coordinated buffer-circuit design that combines slew-rate compensation with offset control, highlighting his contribution to semiconductor circuit innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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