Sunnyvale, CA, United States of America

Samir Agrawal

This inventor holds 1 USPTO granted patent. Top assignee: Cadence Design Systems, Inc.. Active years: 2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Samir Agrawal. Retrieved from https://idiyas.com/inventor/samir-agrawal-qk27i4i2

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2015

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1 patent (USPTO):Explore Patents

Title: Samir Agrawal: Innovator in Data Path Cluster Optimization

Introduction

Samir Agrawal is a notable inventor based in Sunnyvale, CA. He has made significant contributions to the field of logic synthesis, particularly in optimizing data path clusters. His innovative work has led to the development of a patent that addresses critical design challenges in circuit logic.

Latest Patents

Samir Agrawal holds a patent titled "Methods and apparatus for data path cluster optimization." This invention outlines a method of logic synthesis that includes generating multiple design architecture alternatives for circuit logic within a data path cluster. The process involves saving these alternatives and evaluating them against design constraints to select the most suitable architecture. He has 1 patent to his name.

Career Highlights

Samir Agrawal is currently employed at Cadence Design Systems, Inc., a leading company in electronic design automation. His role involves leveraging his expertise to enhance design methodologies and improve efficiency in circuit design.

Collaborations

Throughout his career, Samir has collaborated with talented professionals, including Tsuwei Ku and Jean-Charles Giomi. These collaborations have contributed to the advancement of innovative solutions in the field of electronic design.

Conclusion

Samir Agrawal's work in data path cluster optimization exemplifies the impact of innovation in technology. His contributions continue to shape the future of circuit design and logic synthesis.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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