Katsuta, Japan

Sakae Yaita

This inventor holds 1 USPTO granted patent. Top assignee: Hitachi, Ltd.. Active years: 1996.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sakae Yaita. Retrieved from https://idiyas.com/inventor/sakae-yaita

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 1996

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1 patent (USPTO):Explore Patents

Title: Sakae Yaita: Innovator in Semiconductor Technology

Introduction

Sakae Yaita is a notable inventor based in Katsuta, Japan. He has made significant contributions to the field of semiconductor technology, particularly through his innovative patent.

Latest Patents

Yaita holds a patent for an "Aperture plate and a method of manufacturing the same." This invention involves a semiconductor substrate that features multiple chip portions and chip separating portions. These portions are designed to partition the chip portions from one another. The etching process on both sides of the semiconductor substrate allows for stencil patterns to be exposed, enabling the chip portions to be substantially separated.

Career Highlights

Sakae Yaita is associated with Hitachi, Ltd., a leading company in technology and innovation. His work at Hitachi has allowed him to focus on advancing semiconductor manufacturing techniques.

Collaborations

Yaita has collaborated with notable colleagues, including Teruyuki Kagami and Niro Katane, who contribute to the innovative environment at Hitachi.

Conclusion

Sakae Yaita's contributions to semiconductor technology through his patent demonstrate his commitment to innovation in the field. His work continues to influence advancements in semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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