Austin, TX, United States of America

Sajosh Janarthanam

This inventor holds 2 USPTO granted patents. Top assignee: Advanced Micro Devices Corporation. Active years: 2008-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sajosh Janarthanam. Retrieved from https://idiyas.com/inventor/sajosh-janarthanam

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 2.4

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2008-2013

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2 patents (USPTO):Explore Patents

Title: Innovations by Sajosh Janarthanam: Pioneering Error Detection and Encryption Testing

Introduction

Sajosh Janarthanam, an accomplished inventor based in Austin, TX, has made significant contributions to the fields of error detection and encryption technologies. With two patents under his name, he showcases a commendable blend of technical expertise and innovative thinking.

Latest Patents

Sajosh's most recent patents reflect his aptitude for solving complex problems with inventive solutions. His first patent, titled "Error Detection in FIFO Queues Using Signature Bits," introduces a mechanism within a first-in, first-out (FIFO) queue that enhances the detection of operational errors. This technology employs signature bits associated with each entry in the queue, thereby ensuring data integrity through an innovative comparison system that triggers error signals when discrepancies are found.

Another notable patent, "Method of Testing the Encryption Function of a Device," presents a method to assess the encryption capabilities of a device under test (DUT). The approach involves preprocessing packet data strings and utilizing an encryption engine with tailored initialization vectors and algorithms, leading to reliable encryption verification through bitwise comparison techniques.

Career Highlights

Currently affiliated with Advanced Micro Devices Corporation (AMD), Sajosh has positioned himself at the forefront of technological advancements. His work at AMD exemplifies his commitment to developing state-of-the-art solutions in the computing industry, particularly in enhancing security and reliability in information systems.

Collaborations

Sajosh has collaborated with several distinguished coworkers, including Jonathan Mercer Owen and Michael J Osborn. Together, they foster a collaborative environment that encourages innovation and the development of cutting-edge technologies to address emerging challenges in the field.

Conclusion

Sajosh Janarthanam stands out as a notable inventor whose innovations in error detection and encryption testing reflect a deep understanding of technology and its applications. His contributions have the potential to influence industry practices, ensuring systems are more reliable and secure. As he continues to innovate, the tech community eagerly anticipates his future endeavors and the impact they will have on advancing computing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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