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For the Inventor, By the Inventor

New Delhi, India

Saiyid Mohammad Irshad Rizvi

This inventor holds 18 USPTO granted patents and 4 published patent applications, primarily in High-Speed Circuit Design. Top assignees: Stmicroelectronics International N.v., Stmicroelectronics (Crolles 2) Sas. Active years: 2012-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Saiyid Mohammad Irshad Rizvi. Retrieved from https://idiyas.com/inventor/saiyid-mohammad-irshad-rizvi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 88.9

Average Co-Inventor Count = 2.2

ph-index = 4

Forward Citations = 36(Granted Patents)


Location History:

  • Greater Noida, IN (2013)
  • New Delhi India, IN (2016)
  • New Delhi, IN (2012 - 2024)

Company Filing History:

goldMedal18 out of 1,256 
 
Stmicroelectronics International N.v.
 patents
silverMedal1 out of 781 
 
Stmicroelectronics (Crolles 2) Sas
 patents
where one patent can have more than one assignee

Years Active: 2012-2026

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Areas of Expertise:
High-Speed Links
Fault Protection Circuit
Schmitt Trigger
Glitch Filter
I2C Transmitter
Biasing Cascode
Reference Voltage Generation
Driver Circuit
Programmable Hysteresis
FDSOI Technology
Level Shifter
Signal Skew Reduction
18 patents (USPTO):Explore Patents
1. 12665592 - Device and method for bulk induced pre-emphasis technique in current mode transmitter for high speed links (2026-06-23),
2. 12506479 - High-voltage fault protection circuit (2025-12-23),
3. 12494773 - Schmitt trigger with pull-up transistor (2025-12-09),
4. 11923855 - Schmitt trigger with pull-up transistor (2024-03-05),
5. 11522521 - Glitch filter having a switched capacitance and reset stages (2022-12-06),
6. 11075624 - Hybrid driver having low output pad capacitance (2021-07-27),
7. 10848147 - High performance I2C transmitter and bus supply independent receiver, supporting large supply voltage variations (2020-11-24),
8. 10454466 - Biasing cascode transistors of an output buffer circuit for operation over a wide range of supply voltages (2019-10-22),
9. 10224922 - Biasing cascode transistor of an output buffer circuit for operation over a wide range of supply voltages (2019-03-05),
10. 9762243 - Apparatus for reference voltage generation for I/O interface circuit (2017-09-12),
11. 9473135 - Driver circuit including driver transistors with controlled body biasing (2016-10-18),
12. 9467125 - CMOS Schmitt trigger circuit and associated methods (2016-10-11),
13. 9397622 - Programmable hysteresis comparator (2016-07-19),
14. 9264045 - Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology (2016-02-16),
15. 8981817 - Operating conditions compensation circuit (2015-03-17),

Title: Saiyid Mohammad Irshad Rizvi - Pioneering Inventor from New Delhi

Introduction: Saiyid Mohammad Irshad Rizvi is a distinguished inventor hailing from New Delhi, India, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Saiyid Mohammad Irshad Rizvi holds several patents in various technological domains, showcasing his versatility and ingenuity in creating novel solutions to complex problems.

Career Highlights: With a career spanning over two decades, Rizvi has consistently pushed the boundaries of innovation, leading to the development of cutting-edge technologies that have revolutionized industries.

Collaborations: Throughout his career, Saiyid Mohammad Irshad Rizvi has collaborated with leading research institutions, universities, and tech companies, fostering a culture of innovation and knowledge-sharing.

Conclusion: Saiyid Mohammad Irshad Rizvi's relentless pursuit of innovation and his passion for creating transformative technologies have solidified his reputation as a visionary inventor in the global tech community.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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