Sagar V Reddy

Title: Innovations of Sagar V Reddy

Introduction

Sagar V Reddy is an accomplished inventor based in Santa Clara, CA. He holds a total of four patents, showcasing his expertise in memory architecture and inter-chip communication technologies. His innovative contributions have significantly impacted the field of electronics and computing.

Latest Patents

One of his latest patents is titled "Low standby leakage implementation for static random access memory." This patent discloses a memory architecture designed to optimize leakage currents during standby mode. The architecture comprises multiple memory segments that can operate in various modes, including decoder slices with wordlines and power headers to control leakage currents.

Another notable patent is "Inter-chip input-output (IO) for voltage-stacked near threshold computing (NTC) chips." This invention presents a voltage-stacked system that facilitates inter-chip communication using simple wire interconnections. The system includes secondary supply and ground voltages that are tapped in a predefined sequence to generate internal voltages within the chips, enhancing their operational efficiency.

Career Highlights

Sagar has worked with prominent companies such as Sun Microsystems, Inc. and Dxcorr Design Inc. His experience in these organizations has contributed to his development as a leading inventor in his field.

Collaborations

Throughout his career, Sagar has collaborated with talented individuals, including Shashank Shastry and Ajay Bhatia. These collaborations have fostered innovation and creativity in his projects.

Conclusion

Sagar V Reddy's contributions to the field of electronics through his patents and collaborations highlight his role as a significant inventor. His work continues to influence advancements in memory architecture and inter-chip communication technologies.