The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
Jul. 02, 2007
Sagar V. Reddy, Santa Clara, CA (US);
Sagar V. Reddy, Santa Clara, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A memory is disclosed having one or more logic level reinforcement circuits (LLRC's) coupled to each wordline. Each LLRC has an input and an output, both of which are coupled to a corresponding wordline. The LLRC senses a present logic level on the wordline. If the present logic level is a first logic level, then the LLRC outputs a first logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. If the present logic level is the second logic level, then the LLRC outputs a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. By doing so, the LLRC compensates for the undesirable effects of gate leakage, and enables the memory to operate effectively and efficiently despite the gate leakage.