Sun Microsystems, Inc.

Dxcorr Design Inc.

Sagar V Reddy

Ajay Bhatia

Shashank Shastry

Rajesh Tiruvuru

Sudarshan Kumar

Mayank Tayal

A memory architecture for optimizing leakage currents in standby mode and a method thereof is disclosed. The memory architecture includes a plurality of memory segments configured to operate in one or more modes of operations. The plurality of memory segments includes a plurality of decoder slices. Each of the plurality of decoder slice includes a plurality of wordlines running in the row direction; at least one array power header configured for controlling leakage currents within each of the plurality of decoder slice in the row direction; and a retention header. Each of the plurality of power supply rails running in the column direction are segmented within one or more decoder slice to form one or more segmented power supply node.

Low standby leakage implementation for static random access memory

A voltage stacked system that includes a stack of near threshold computing (NTC) chips for achieving inter-chip communication with simple wires as interconnections is disclosed. The chips include at least two secondary supply voltages and at least a secondary ground voltage electrically coupled to the stack of the chips arranged in series. The secondary supply and ground voltages are tapped in a predefined sequence at one or more predefined access points in the stack to generate two versions of an internal voltage within each of the chips. Each of the two versions of the internal voltage is a voltage difference between respective supply voltages and ground voltages, and the two have a set voltage shift such that the chips in the stack have supply voltages overlapping with those in the neighboring chips. Optionally, the two voltages are boosted to further higher voltages as needed using charge pumps.

Inter-chip input-output (IO) for voltage-stacked near threshold computing (NTC) chips

A memory is disclosed having one or more logic level reinforcement circuits (LLRC's) coupled to each wordline. Each LLRC has an input and an output, both of which are coupled to a corresponding wordline. The LLRC senses a present logic level on the wordline. If the present logic level is a first logic level, then the LLRC outputs a first logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. If the present logic level is the second logic level, then the LLRC outputs a second logic level reinforcement signal onto the wordline to push the voltage on the wordline towards a desired voltage for that logic level. By doing so, the LLRC compensates for the undesirable effects of gate leakage, and enables the memory to operate effectively and efficiently despite the gate leakage.

Mechanism for compensating for gate leakage in a memory

A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line.

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Santa Clara, CA, United States of America

Sagar V Reddy