This inventor holds 5 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2002-2005.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Location History:
- Santa Clara, CA (US) (2002 - 2003)
- Los Altos, CA (US) (2003 - 2005)
Company Filing History:
Years Active: 2002-2005
Title: Sadhana Madhyastha - Innovator in Memory Technology
Introduction
Sadhana Madhyastha is a prominent inventor based in Los Altos, California. She has made significant contributions to the field of memory technology, holding a total of five patents. Her work focuses on enhancing the efficiency and performance of memory systems.
Latest Patents
One of her latest patents is titled "Word line transistor stacking for leakage control." This innovation involves a memory system, such as a register file or cache, that utilizes stack pMOSFETs shared among its word line drivers. The design allows for reduced sub-threshold leakage current while maintaining performance. Another notable patent is the "Low power precharge scheme for memory bit lines." This scheme introduces a low power precharge method that optimizes memory bit line operations during read and write processes.
Career Highlights
Sadhana currently works at Intel Corporation, where she continues to push the boundaries of memory technology. Her expertise and innovative mindset have made her a valuable asset to the company.
Collaborations
Throughout her career, Sadhana has collaborated with talented individuals such as Sudarshan Kumar and Jiann-Cherng James Lan. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.
Conclusion
Sadhana Madhyastha's contributions to memory technology exemplify her dedication to innovation. Her patents
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile