Hyogo, Japan

Ryuji Omura

This inventor holds 3 USPTO granted patents. Top assignee: Other. Active years: 2001-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ryuji Omura. Retrieved from https://idiyas.com/inventor/ryuji-omura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 81(Granted Patents)


Location History:

  • Tokyo, JP (2002)
  • Hyogo, JP (2001 - 2003)

Company Filing History:

goldMedal3 out of 834,570 
Other
 patents

Years Active: 2001-2003

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3 patents (USPTO):Explore Patents

Title: Ryuji Omura: Innovator in Semiconductor Testing Technology

Introduction

Ryuji Omura is a notable inventor based in Hyogo, Japan. He has made significant contributions to the field of semiconductor testing, holding a total of 3 patents. His work focuses on improving the efficiency and cost-effectiveness of testing semiconductor devices.

Latest Patents

One of Ryuji Omura's latest patents is a semiconductor testing apparatus designed for testing semiconductor devices that include a built-in self-test circuit. This innovative apparatus allows a program power supply of a tester to apply a power supply voltage to an integrated circuit (IC) being tested. A pattern generator applies a clock signal and a command signal to the built-in self-test (BIST) circuit of the IC. The BIST circuit tests both memory IC units and logic IC units, serially outputting data indicative of the test results to a converter of the tester. This converter then transforms the applied serial data into parallel data for application to a computer. Compared to prior art, this method reduces the number of pins necessary for testing, thereby lowering costs and improving testing efficiency.

Another significant patent by Omura is related to a repair analysis circuit for redundancy, a redundant method for repairing redundancy, and a semiconductor device. This invention shortens the time required for testing defective memory cells and eliminates the need for failure memories with large capacities for storing defective bits. The design allows for easy adaptation to increases and decreases in input/output (IO) numbers. A large number of IO outputs are collectively compared with a specified expected value, resulting in judgment information that is outputted to an error information acquiring device. This innovative approach enables repair analysis without relying on defective redundant memory cells.

Career Highlights

Ryuji Omura has established himself as a key figure in semiconductor technology through his inventive work. His patents reflect a deep understanding of the challenges faced in semiconductor testing and a commitment to developing solutions that enhance performance and reduce costs.

Collaborations

Ryuji has collaborated with notable colleagues, including Kazushi Sugiura and Mari Shibayama. Their combined expertise contributes to the advancement of semiconductor technology and innovation.

Conclusion

Ryuji Omura's contributions to semiconductor testing technology demonstrate his innovative spirit and dedication to improving industry standards. His patents not only enhance testing efficiency but also pave the way for future advancements in

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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