North York, Canada

Ruolong Lian

This inventor holds 1 USPTO granted patent. Top assignee: Microsemi Soc Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ruolong Lian. Retrieved from https://idiyas.com/inventor/ruolong-lian-a0togsa9

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ruolong Lian and RISC-V SoC Generation

Introduction

Ruolong Lian is an inventor associated with North York, Canada, and Microsemi Corporation. His listed patent focuses on combining software execution with hardware acceleration in a system-on-chip built around an open-standard processor.

Latest Patents

Lian is credited with 1 patent: “High-Level Synthesis for RISC-V System-on-Chip Generation for Field Programmable Gate Arrays.” The patent describes instructions that analyze a code stream and divide its work between software running on an open-standard processor and hardware accelerators implemented in reprogrammable hardware. The system compiles the software portion into a binary and generates a hardware description for the accelerator portion, enabling both to exchange data while the code runs.

Career Highlights

The patent reflects work on high-level synthesis and automated generation of RISC-V system-on-chip designs for field-programmable gate arrays. Its approach aims to assign suitable tasks to processor software or hardware accelerators.

Collaborations

Lian’s listed coworkers include Jongsok Choi and David Ma. The patent’s described system brings together processor-based software and reprogrammable hardware acceleration.

Conclusion

Ruolong Lian’s patent contribution centers on generating RISC-V-based SoC designs that coordinate compiled software with hardware accelerators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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