San Jose, CA, United States of America

Roy K Yamanouchi

This inventor holds 4 USPTO granted patents. Top assignee: National Semiconductor Corporation. Active years: 1983-1993.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Roy K Yamanouchi. Retrieved from https://idiyas.com/inventor/roy-k-yamanouchi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.4

ph-index = 3

Forward Citations = 72(Granted Patents)


Company Filing History:


Years Active: 1983-1993

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4 patents (USPTO):Explore Patents

Title: Roy K. Yamanouchi: Innovator in Integrated Circuit Design

Introduction

Roy K. Yamanouchi is a notable inventor based in San Jose, CA, who has made significant contributions to the field of integrated circuit design. With a total of 4 patents to his name, Yamanouchi has developed innovative methodologies that enhance the efficiency and effectiveness of circuit design processes.

Latest Patents

One of Yamanouchi's latest patents is titled "Structured Logic Design Method Using Figures of Merit and a Flowchart." This invention provides a structured integrated circuit design methodology that describes a two-phase logic function using a high-level behavioral description flow chart. The methodology focuses on properly sizing devices for speed and reducing trial and error in circuit layout implementation through novel chip planning techniques. It begins with defining signal types based on the circuit function and establishes a rigid set of rules for their use. The technical specifications of the two-phase logic function are then defined to create a behavioral flow chart, which is supported by a database of corresponding Boolean equations. These equations are converted into a logic diagram, which is analyzed for speed using a Figures of Merit technique. The resulting circuit design can be carried through to layout using conventional computer-aided design (CAD) tools.

Another significant patent is the "Single Device Transfer Static Latch." This invention involves a static latch implemented in MOS transistor circuitry. Each cell of the static latch includes an MOS transistor configured to operate in depletion mode, allowing for efficient data writing to the cell. The presence of a control signal enables a transfer gate to establish a communication path for data while disabling the MOS transistor to terminate communication during the write operation.

Career Highlights

Roy K. Yamanouchi is currently employed at National Semiconductor Corporation, where he continues to innovate in the field of semiconductor technology. His work has had a lasting impact on the design and functionality of integrated circuits.

Collaborations

Yamanouchi has collaborated with notable coworkers, including Robert Walter Williams and D. Kevin Covey, contributing to advancements in their respective fields.

Conclusion

Roy K. Yamanouchi's contributions to integrated circuit design through his innovative patents demonstrate his expertise and commitment to advancing technology. His work continues to influence the semiconductor industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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