logo

For the Inventor, By the Inventor

Essex Junction, VT, United States of America

Robert L Barry

This inventor holds 19 USPTO granted patents and 9 published patent applications, plus 1 CIPO patent. Top assignees: International Business Machines Corporation, Globalfoundries Inc., Globalfoundries U.S. 2 LLC. Active years: 1986-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Robert L Barry. Retrieved from https://idiyas.com/inventor/robert-l-barry

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 19 

% Patents Active = 84.2


Average Co-Inventor Count = 2.5

ph-index = 5

Forward Citations = 84(Granted Patents)


Location History:

  • Pleasant Valley, NY (US) (1986 - 1991)
  • Essex Junction, VT (US) (1997 - 2021)

Company Filing History:

goldMedal17 out of 166,351 
 
International Business Machines Corporation
 patents
silverMedal1 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 59 
 
Globalfoundries U.S. 2 LLC
 patents

Years Active: 1986-2021

Loading Chart...
Loading Chart...
19 patents (USPTO):Explore Patents
1. 11011295 - High efficiency on-chip 3D transformer structure (2021-05-18),
2. 10049806 - High efficiency on-chip 3D transformer structure (2018-08-14),
3. 9831026 - High efficiency on-chip 3D transformer structure (2017-11-28),
4. 9779869 - High efficiency on-chip 3D transformer structure (2017-10-03),
5. 9431164 - High efficiency on-chip 3D transformer structure (2016-08-30),
6. 9318620 - Folded conical inductor (2016-04-19),
7. 9251948 - High efficiency on-chip 3D transformer structure (2016-02-02),
8. 9171663 - High efficiency on-chip 3D transformer structure (2015-10-27),
9. 8987067 - Segmented guard ring structures with electrically insulated gap structures and design structures thereof (2015-03-24),
10. 8836460 - Folded conical inductor (2014-09-16),
11. 7466284 - Chip seal ring having a serpentine geometry (2008-12-16),
12. 6922349 - Complementary two transistor ROM cell (2005-07-26),
13. 6778419 - Complementary two transistor ROM cell (2004-08-17),
14. 6675273 - Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested (2004-01-06),
15. 5825785 - Serial input shift register built-in self test circuit for embedded (1998-10-20),

Couldn't find inventor

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…