International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Robert L Barry

Venkata Nr Vanukuru

Robert Allen Groves

Steven Michael Eustis

Peter Francis Croce

Venkata N R Vanukuru

John E Andersen

Yabin Wang

John D Chickanosky

Jeffrey P Gambino

Mark David Jaffe

Michael Richard Ouellette

Steven Frederick Oakland

Bradley Alan Orner

Phillip Francis Chapman

Brian Cran

Kevin N Ogg

Michael Lawrence Gautsch

Kenneth Howard Christie

James N Bisnett

Eric G Fung

Dennis J Shea

Daniel Reddy

Erik Henne

Dean Corcoran

An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track included first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including third turns of a third radius within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.

High efficiency on-chip 3D transformer structure

A transformer structure includes at least three sections, each corresponding to metal layers of an integrated circuit. A first section of the at least three sections is electrically coupled to a third section with a second section disposed between the first and third sections. The at least three sections includes inductor coils, all of which are wound in a same direction and voltage phase starting at an outer terminal and continuing to an inner terminal of each inductor coil. At least one radial wiring channel passes through a portion of a coil in one of the three sections to provide an external connection to an internal terminal of the coil in at least one of the three sections.

A transformer structure includes a first coil having two sections of spiral, with a top section including a plurality of metal layers occupying top X metal layers and a bottom section including a plurality of metal layers occupying bottom Z metal layers, where X and Z represent a number of metal layers having a specific number selected to provide a particular performance of the first coil. A second coil of the transformer is disposed between the two sections of the first coil and includes a plurality of metal layers where Y represents a number of vertically adjacent metal layers, with the specific number chosen to provide the particular performance, such that a sum X+Y+Z represents a total number of vertical metal layers for the transformer structure.

A semiconductor inductor structure may include a first spiral structure, located on a first metal layer, having a first outer-spiral electrically conductive track and a first inner-spiral electrically conductive track separated from the first outer-spiral electrically conductive track by a first dielectric material. A second spiral structure, located on a second metal layer, having a second outer-spiral electrically conductive track and a second inner-spiral electrically conductive track separated from the second outer-spiral electrically conductive track by a second dielectric material may also be provided. The first outer-spiral electrically conductive track may be electrically coupled to the second outer-spiral electrically conductive track and the first inner-spiral electrically conductive track may be electrically coupled to the second inner-spiral electrically conductive track. The first outer-spiral conductive track is laterally offset relative to the second outer-spiral conductive track and the first inner-spiral conductive track is laterally offset relative to the second inner-spiral conductive track.

Folded conical inductor

An integrated circuit transformer structure includes at least two conductor groups stacked in parallel in different layers. A first spiral track is formed in the at least two conductor groups, the first spiral track includes first turns of a first radius within each of the at least two conductor groups, and second turns of a second radius within each of the at least two conductor groups, the first and second turns being electrically connected. A second spiral track is formed in the at least two conductor groups, the second spiral track including a plurality of adjacent turns of one or more radii within each of the at least two conductor groups and disposed in a same plane between the first and second turns in each of the at least two conductor groups.

Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure.

Segmented guard ring structures with electrically insulated gap structures and design structures thereof

A chip seal ring that maintains the chip seal ring as a continuous barrier to contamination, while at the same time creating a desirable electrical feature in the seal ring that enables the use of an on-chip loop antenna. In one embodiment, at least a portion of the chip seal ring has a serpentine configuration, such as a square wave, triangle wave, or curved geometry, that increases the reactance and resistance of the seal ring so as to mitigate the adverse induced currents created by the magnetic coupling effects between the on-chip antenna and the seal rings, thereby improving the efficiency of an on-chip loop antenna in the presence of the seal ring.

Chip seal ring having a serpentine geometry

A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.

Complementary two transistor ROM cell

A memory circuitry is designed to efficiently obtain a predictable array output when an invalid address is requested. The memory circuit comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.

Memory circuitry with auxiliary word line to obtain predictable array output when an invalid address is requested

A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

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Essex Junction, VT, United States of America

Robert L Barry