Ritesh P Turakhia

Title: Ritesh P Turakhia: Innovator in Integrated Circuit Testing

Introduction

Ritesh P Turakhia is a notable inventor based in Portland, OR (US). He has made significant contributions to the field of integrated circuit testing, holding 2 patents that showcase his innovative approaches to detecting defects in semiconductor devices.

Latest Patents

One of his latest patents is titled "Method for generating test patterns for small delay defects." This method involves generating a traditional delay fault pattern, fault grading it for small delay defect coverage, and reporting faults detected along with associated delay information. The process also includes determining timing-aware target faults and generating timing-aware delay fault patterns for these targets.

Another significant patent is "Methods of screening ASIC defects using independent component analysis of quiescent current measurements." This method utilizes measurements of quiescent current for each die in a sample lot to generate a test matrix. It employs independent component analysis to model passing die and establishes statistical limits for quiescent current to identify defects effectively.

Career Highlights

Ritesh has worked with prominent companies in the semiconductor industry, including LSI Corporation and LSI Logic Corporation. His experience in these organizations has contributed to his expertise in integrated circuit design and testing.

Collaborations

Ritesh has collaborated with notable professionals in his field, including Sandeep Kumar Goel and Narendra B Devta-Prasanna. These collaborations have likely enriched his work and led to further advancements in integrated circuit technology.

Conclusion

Ritesh P Turakhia is a distinguished inventor whose work in integrated circuit testing has led to innovative methods for defect detection. His contributions continue to impact the semiconductor industry positively.